2.5 and 3D Integration is becoming a reality in device manufacturing. A critical process step is the thinning of the silicon wafer to reveal the metal filled Through Silicon Via (TSV). Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes chemical mechanical planarization (CMP) and plasma etching has been used to complete the final thinning of the silicon. However, this conventional process has a number of disadvantages associated therewith including but not limited to the complexity of the process and the associated costs. As described hereinafter, the present invention is directed at overcoming these deficiencies associated with the conventional process by providing a simple, cost effective method to wet etch the remaining silicon to reveal the TSVs.
TSV wafers (wafers are also referred to herein as substrates) are manufactured by creating vias (holes) in the top surface of the wafer. These vias extend part way through the thickness of the wafer. The holes are then filled in with a conductive material (studs), with or without an insulating liner. The conductor-filled vias are referred to herein as TSVs. The bottom side of the wafer, opposite of where the TSVs were created, is then put through a grind process where mechanical grinding reduces the thickness of the substrate, effectively reducing the distance from the bottom of the via to the bottom surface of the substrate. Complete grinding of the substrate to expose the conductor is undesired as this would result in ions from the conductive material being smeared across the substrate surface, thereby altering the electrical properties at the contaminated sites and reducing yield. Any number of manufacturing steps can be performed on the top side of the wafer prior to further processing of the bottom side depending on the application. For example, for a device wafer, the full device structure and metallurgical components can be added to the top surface of the wafer. For 2.5D interposer applications, the top side wiring/interconnects can be completed. The wafer with TSVs is then typically mounted using an adhesive layer on a carrier wafer with the top of the wafer toward the carrier wafer.
The grinding process leaves a layer of substrate material above the TSVs that can have variations in thickness that is radially dependent, for instance, thicker at the edge of the wafer, uniform across the wafer or thicker at the center of the wafer than at the edge (within wafer thickness variation). Likewise there can be a difference in height of the substrate material above the TSVs on a wafer to wafer basis (wafer to wafer thickness variation). These differences in the layer above the TSVs can be greater than the allowable difference in height of the exposed TSVs.
Integrated circuit wafers, which typically are in the form of flat round disks (although other shapes are possible) and often are made from silicon, Gallium Arsenide, or other materials, may be processed using various chemicals. One process is the use of liquid chemical etchant to remove material from or on the substrate, this process is often referred to as wet etching. Commonly used methods include submerging the wafers in chemical baths (referred to as “batch processing” or “immersion processing”), or dispensing fluid on a wafer while spinning (referred to as “single wafer processing”). As wafer sizes increase and geometry sizes decrease, substantial benefits can be realized by employing single wafer processing inasmuch as the processing environment may be better controlled.
The etch rate of wet etch process will vary with changes in etchant concentration. The addition of small amounts fresh chemical etchant to sustain the etch rate is a common practice when the chemical etchant is recirculated. Typically the addition is based on a mathematical model based on wafers processed or elapsed time from etchant preparation. If there is no measurement feedback the etch rate will hold only as well as the mathematical model can predict the need to inject fresh chemical etchant. Likewise any external influences will not be accounted for and the etch rate will not remain constant. The depth of the etch process is a function of etch rate and time. Time is well controlled but the etch rate can vary based on several factors. Likewise the required depth to etch will vary as there will be within wafer thickness variation and wafer to wafer thickness variations. The foregoing impacts the ability of existing wet-etching process systems to precisely etch wafers to the desired thickness and uniformity and consistently in a production environment. Accordingly the lack of a method to process wafers according to etch recipes that are accurately tailored to the amount of material to be removed from each wafer limits the capability of existing systems to expose a precise depth on each wafer processed.
Similar to thinning TSV wafers, the conventional process for thinning non TSV wafers involves grinding to remove the bulk of the wafer and a multistep sequence of processes that includes chemical mechanical planarization (CMP) and plasma etching to complete the final thinning of the wafer. However, this conventional process has a number of disadvantages associated therewith including but not limited to the complexity of the process and the associated costs. As described hereinafter, the present invention is directed at overcoming these deficiencies associated with the conventional process by providing a simple, cost effective method to wet etch the remaining substrate to a desired thickness and surface uniformity. Thus, there exists a need for a system and method for: (1) determining quantity and pattern of material to be removed from the substrate; (2) removing the material to the desired depth and uniformity efficiently in a production environment. The present invention achieves these objectives as described below.